AMD to launch Zen 6 Epyc server CPUs at Advancing AI event in late July

AMD will begin its Zen 6 rollout with server-class Epyc processors at its Advancing AI event on July 22-23, 2026, as confirmed by CTO Mark Papermaster. Desktop variants are expected later, possibly in 2027.

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AMD is set to launch its next-generation Zen 6 processor architecture at the company's Advancing AI event in San Francisco on July 22 and 23, 2026, starting with server-grade Epyc chips, according to chief technology officer Mark Papermaster.

Papermaster told SiliconANGLE Media that the company plans to bring "a leading x86 CPU of the new generation" to market at the event. He emphasized the importance of the x86 ecosystem for enterprise customers, noting that enterprises have "decades of running x86" and "They're not going to move that install base."

The initial Zen 6 products are the Epyc 9006 series, codenamed Venice, which will succeed the Epyc 9005 Turin generation. AMD has previously stated that Venice chips will be manufactured using TSMC's 2nm process node, a first for high-performance computing processors. The top configuration is expected to feature up to 256 Zen 6 cores across eight CCDs, representing a 33% increase over the current 192-core Turin chips. Memory throughput is claimed to reach 1.6 terabytes per second, and AMD is promising a 70% performance boost over Zen 5-based chips.

Initial production will take place at TSMC's facilities in Taiwan, with future manufacturing also planned at TSMC's Arizona fab. The Venice platform is rumored to use a new SP7 socket, with early units shown at Computex suggesting support for PCIe 6.0 and 16-channel memory, compared to the SP5 platform's 12 channels and PCIe 5.0.

Desktop consumers will not see Zen 6 at the July event. No Ryzen products are expected, and leaks indicate the desktop lineup, codenamed Olympic Ridge, may not arrive until 2027, with a possible reveal at CES 2027 in January. Leaked specifications suggest desktop Zen 6 chips could offer up to 24 cores and up to 288 MiB of L3 cache with 3D V-Cache on two CCDs, while retaining the AM5 platform and using TSMC's 2nm node. Some rumors also claim AMD may drop the integrated GPU in favor of an NPU with CUDIMM support.