AMD Enters Rack-Scale AI Era with Helios and MI455X, Challenging Nvidia Dominance

AMD unveiled its Instinct MI455X GPU and Helios rack-scale system at Advancing AI 2026, aiming to rival Nvidia with open standards and competitive specs, though software and delivery timelines remain hurdles.

This article was drafted with AI assistance from multiple sources and was reviewed and approved by a human editor before publication.

At its Advancing AI 2026 event on July 22-23, AMD introduced the Instinct MI455X GPU and the Helios rack-scale architecture, marking its first direct challenge to Nvidia's dominance in large-scale AI deployments.

The MI455X packs 320 billion transistors, built using a chiplet design: four compute chiplets (XCDs) on two foundation dies (FCDs) with hybrid bonding, plus two I/O dies and 12 HBM4 stacks, all assembled with CoWoS-L packaging. The XCDs are manufactured on TSMC's 2N GAA process, while the FCDs and I/O dies use TSMC N3P.

AMD's CDNA 5 architecture introduces several changes: the basic building block is now called a Work Group Processor (WGP), replacing the Compute Unit, with 256 WGPs per MI455X—the same count as the MI355X. The wavefront size has been reduced from 64 to 32 threads. A new Transcendental Unit doubles throughput compared to CDNA 4 and adds an explicit tanh instruction.

In terms of memory, the cache hierarchy includes 96 MB of L2 cache per FCD (192 MB total), with no Infinity Cache, and L2 bandwidth is three times that of the MI355X. Local Data Share (LDS) per WGP doubles to 320 KB, resulting in 96 MB of total LDS across the chip—twice the MI355X. The MI455X features 12 HBM4 stacks, offering 432 GB capacity and 23.3 TB/s bandwidth per GPU.

AMD claims the MI455X achieves a theoretical peak of 40.26 PF in OCP MXFP4 format, which it says surpasses Nvidia's Rubin at 35 PF in NVFP4 dense mode. Other peak performance figures include 20.13 PF in OCP MXFP6 and OCP MXFP8, 5.03 PF in Matrix FP16/BF16, and 315 TF in Vector FP16, Matrix FP32, and Vector FP32.

The Helios rack-scale system integrates 72 MI455X GPUs per rack with 18 EPYC Venice CPUs (one per four GPUs) and 31 TB of HBM4 total. It uses UALink with 256 GB/s per direction and external connectivity of 12x 800 Gb Ethernet per slot. The rack price ranges from $5 million to $5.5 million depending on configuration.

AMD also unveiled the EPYC 9996 Venice CPU, featuring 256 Zen 6 cores, 512 threads, 1 GB L3 cache, a 600 W TDP, and boost clock up to 4.1 GHz (2.55 GHz base), built on TSMC's 2nm process. The EPYC 9006 series supports up to 16 memory channels, MRDIMM up to 12,800 MT/s, and PCIe Gen 6. AMD claims the EPYC 9996 is up to 3.4 times ahead of Intel's Xeon competitor and about 20 percent ahead of Nvidia's Vera, based on manufacturer benchmarks.

Engineering samples of the MI455X are expected in the second half of 2026, with volume production slated for Q2 2027. Microsoft will receive early hardware for Azure in H2 2026, and general availability is expected in spring 2027. Key customers include Microsoft, Oracle, and Meta, while Anthropic has committed to over one million AMD GPUs.

AMD also announced a partnership with Cerebras for fast inference and outlined its future roadmap: the MI400 series and then MI500 in 2027, with CPU generations Venice (Zen 6), Florence (Zen 7), and Ravenna (Zen 8).

Despite the aggressive push, AMD faces challenges in software ecosystem maturity and delivery timelines as it takes on Nvidia's established NVL72 platform with Blackwell and Rubin architectures.